What is PCB insertion loss?#
PCB insertion loss describes the reduction in transmitted signal power through an interconnect, expressed in decibels. It applies to the complete path being evaluated: traces, vias, connector launches and other structures between the chosen reference planes. It is not a phenomenon that suddenly begins at 3 GHz, and it is not caused only by impedance mismatch.
In a matched two-port measurement with equal reference impedances, forward transmission is represented by S21. A network analyzer commonly plots 20 log10|S21|, which is negative for a lossy passive path. When insertion loss is reported as a positive loss value, the sign is reversed: IL = -20 log10|S21|. For example, an S21 magnitude of -3 dB corresponds to approximately 3 dB of insertion loss. Always check the convention used in a graph or specification.
Why insertion loss matters#
A channel must deliver enough signal to its receiver over the required frequency range. Different attenuation across that range changes the received waveform rather than simply scaling every part of it equally. For a digital interface, assess the channel against the relevant interface requirements and receiver capability; a clock frequency alone does not describe all the frequency content of its edges.
Record the trace length, layer, reference planes and endpoints when discussing a loss result. A value from a short material coupon is not interchangeable with the result for an entire assembled channel. A useful specification states the frequency range, maximum permitted loss, measurement convention and the structures included.
What contributes to PCB insertion loss?#
- Conductor loss: finite conductivity and current distribution in the copper cause dissipation. Copper surface roughness can increase high-frequency conductor loss; choosing smoother foil does not eliminate skin effect.
- Dielectric loss: the insulating material dissipates energy. Dissipation factor, Df or loss tangent, characterizes this behavior. Dielectric constant, Dk, affects propagation and impedance but is not the same as Df.
- Mismatch and discontinuities: changes at vias, pads and connectors can reflect energy and reduce forward transmission. Their effect depends on geometry and the surrounding reference structure.
- Other mechanisms: radiation and leakage may also contribute, depending on the construction and operating conditions.
There is no universal frequency boundary at which mismatch stops dominating and dielectric loss takes over. The balance depends on material, geometry, copper roughness, length and transitions. Compare the actual stack-up and channel rather than assigning a cause from frequency alone.
Insertion loss versus return loss#
S21 describes forward transmission; S11 describes reflection at the input. Return loss is conventionally -20 log10|S11|, so a larger positive return-loss value means less reflection. This is the opposite direction from positive insertion loss, where a smaller value means less transmission loss.
Use both results when diagnosing a channel. A low transmitted signal does not by itself reveal how much energy was reflected and how much was dissipated. A connector must be evaluated together with its PCB launch: pad dimensions, reference-plane treatment and via geometry are part of the transition.
A practical design and validation workflow#
- Define the interface requirement, channel endpoints and loss budget before selecting the laminate.
- Ask the fabricator for a manufacturable stack-up and material data at relevant test conditions. Compare Dk and Df separately rather than choosing a material only because its Dk is low.
- Keep unnecessary routing length and transitions out of the critical path. Review connector footprints and via structures as part of the channel model.
- Evaluate material and geometry changes with a suitable model, then compare representative hardware using the same measurement setup.
- Agree on calibration, reference planes and treatment of fixtures before accepting a test report. Do not compare measurements that include different cables or launches as if they describe the same PCB.
- Put the approved material, geometry and acceptance requirements into revision-controlled manufacturing documents.
Use our Gerber viewer to inspect the manufacturing layers, and the PCB testing guide to distinguish fabrication checks from channel-performance measurements. For a build discussion, send the relevant requirements with your files to our PCB assembly team.
Frequently asked questions#
Does low Dk automatically mean low insertion loss?
No. Dk and Df describe different material properties. Evaluate dielectric loss, conductor behavior and the complete channel geometry together.
Can impedance control eliminate insertion loss?
No. Controlling impedance helps manage reflections, but a matched real interconnect still has dissipative losses.
Is a negative S21 reading an error?
Not necessarily. Negative logarithmic transmission is normal for a passive lossy path. Confirm whether the display shows S21 in dB or a positive insertion-loss value.
Can I reuse one loss limit for every PCB?
Only if it matches the interface, path length, endpoints and qualification conditions. Define acceptance for the actual product rather than copying a coupon result.
Technical references: Rogers on circuit materials and high-frequency losses; Keysight network-analyzer measurement parameters; Keysight S21 logarithmic transmission measurement guidance.