The consequences of a poorly designed PDN are significant, ranging from intermittent issues to complete system failures.
We invite you to peruse the information we’ve compiled on this subject. Join us as we explore the crucial aspects of PDN design in PCBs through our guide.
The Significance of PDN in PCB Design#
Maintaining power integrity in PCB design is a challenge that grows with each design iteration. As core voltages decrease to 1.2V and below, the current demands inevitably rise, leading to increased IR drop (IR drop = I * R). Moreover, the push towards more compact electronics necessitates fewer layers and denser circuit designs, leaving less room for power nets. Vias introduce further complications, often creating a “Swiss cheese” effect in power planes.
The life of a PCB designer is strewn with PDN challenges—interpreting varied instructions from hardware designers or power integrity engineers that come through different communication channels such as emails and calls, or conventional wisdom. These directives need to be assimilated and applied across numerous power supplies. After which, the designer faces further requests to minimize size, reduce layers and components, often within impractical timeframes.
Electromagnetic Interference (EMI) Considerations#
As circuit speeds increase, susceptibility to EMI from both internal and external sources can become a more pressing issue. To mitigate EMI-related problems, strategic configuration of power and ground planes can provide effective shielding.
Addressing Ground Bounce Issues#
Concurrently switching digital signals can result in simultaneous switching noise (SSN) or ground bounce. This is a typical occurrence in memory or data buses and can lead to signal levels failing to return to their intended reference ground level, causing them to bounce above it.
Such noise can interfere with proper circuit operation and may induce false switching. A robust PDN minimizes these effects by stabilizing the ground level.
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Managing Power Ripples#
Noise or ripples can also be generated by the power supply’s switching actions, leading to crosstalk in adjacent circuitry and negatively impacting signal integrity in those circuits.
Defining PDN Impedance in PCB#
A PDN encompasses every component connected to the voltage and ground rails, including the power and ground planes, interconnecting buses, decoupling capacitors fostering power stability, and any copper features linking to the primary power rails. The PDN impedance comprises parasitic effects such as capacitance and inductance from connections to integrated circuits (ICs).
Key parasitic elements that significantly influence PDN impedance include:
- Plane Capacitance – Capacitance existing between the PDN’s plane layers.
- Capacitor Inductance – Parasitic inductance from capacitor leads, affecting self-resonance.
- Trace Inductance – Inductive contributions from power-delivering traces to the overall PDN.
Why PDN Impedance Matters in PCB Design#
The importance of PDN impedance is well known among high-speed and high-frequency designers, and soon enough, all designers will need to adopt this knowledge with advancing technology. Here we consolidate the crucial impact of PDN impedance on PCB behavior:
Power Bus Noise Implications#
Transient currents can cause voltage fluctuations or ripples within your PCB, which is directly influenced by the PDN’s impedance profile across different frequencies.
Damping of Power Bus Oscillations#
Ringing or underdamped oscillations might become evident on the power bus, potentially resulting from improper sizing of decoupling capacitors or neglecting their self-resonance frequencies.
Necessity of Adequate Decoupling#
Traditional capacitors are increasingly unable to provide sufficient decoupling in fast logic PCBs due to their limited self-resonance frequencies (around 100 MHz). To compensate, designers are leveraging interplane capacitance and newer capacitors with self-resonance frequencies in the GHz range to achieve adequate decoupling in high-speed and high-frequency PCB applications.
Practical PDN Design Workflow#
The power-distribution network includes voltage regulators, planes, traces, vias, capacitors, package interconnect and the on-die load. Its impedance must remain low enough across the relevant frequency range to control supply noise.
- Define allowable ripple and convert it into a target impedance.
- Choose stack-up and adjacent power/ground planes to reduce spreading inductance.
- Select capacitors by mounted impedance, not capacitance value alone.
- Place vias and capacitors to minimize loop inductance at high frequency.
- Model anti-resonance and regulator interaction across the full network.
- Measure prototypes with suitable probing and compare results with simulation.
Frequently Asked Questions#
What is PDN target impedance?
It is the maximum acceptable impedance derived from permitted voltage ripple divided by the expected current step.
Does adding more capacitors always help?
No. Parasitics and resonances can create impedance peaks. Value, package, placement and mounting geometry matter.
Why place power and ground planes close together?
A small dielectric separation increases plane capacitance and reduces loop inductance, improving high-frequency behavior.